The present application relates to a variable capacitance device, and particularly to a variable capacitance device having a variable capacitance element in which a plurality of electrodes are laminated via dielectric layers.
Variable capacitance elements for controlling voltage and/or current are used in various electronic devices in the past. Various techniques have been proposed to obtain higher-performance elements in such variable capacitance elements (see Japanese Patent Laid-Open No. 2008-66682, Japanese Patent Laid-Open No. 2009-142043 and Japanese Patent Laid-Open No. 2009-16613 for example (hereinafter referred to as Patent Document 1, 2 and 3, respectively)).
Patent Document 1 proposes a variable capacitor including a first capacitance section in which a plurality of first capacitance electrodes and a plurality of first bias electrodes (control electrodes) are laminated alternately via a dielectric. The variable capacitor also includes a second capacitance section in which a plurality of second capacitance electrodes and a plurality of second bias electrodes are laminated alternately via a dielectric. The variable capacitor further includes a variable capacitance section in which a first bias electrode and a second bias electrode are opposed to each other via a dielectric. In Patent Document 1, the variable capacitor is formed as described above, whereby bias voltage is lowered and a rate of capacitance change is increased.
Patent Document 2 proposes a power controlling circuit for controlling input alternating-current power using a variable capacitor. In the power controlling circuit of Patent Document 2, a plurality of electrodes are laminated via a dielectric, and the electrodes are appropriately connected to an alternating-current power supply 2 and a control power supply 3 such that an equivalent circuit as shown in FIG. 20 is obtained, for example.
In the power controlling circuit 850 of Patent Document 2 shown in FIG. 20, a pair of series circuits each including two variable capacitors connected in series with each other is formed, and a point of connection between the two capacitors within each series circuit is connected to the alternating-current power supply 2 via external terminals 811 and 812. In addition, in the example shown in FIG. 20, the two series circuits are connected in series with the control power supply 3 via two control terminals 813 and 814 (external terminals). Incidentally, one control terminal 813 is connected to the positive electrode of the control power supply 3 via a DC (Direct Current) removing resistance 821, and the other control terminal 814 is connected to the negative electrode of the control power supply 3 via a DC removing resistance 822.
Patent Document 3 proposes a technique of arranging a plurality of variable capacitors in one dielectric to thereby decrease external terminals and the like and achieve miniaturization. FIGS. 21A to 21C show an example of configuration of a capacitor array proposed in Patent Document 3. Incidentally, FIG. 21A is a schematic top view of the capacitor array, FIG. 21B is a schematic bottom view of the capacitor array, and FIG. 21C is a side view of the capacitor array.
In the example shown in FIGS. 21A to 21C, four upper electrodes 902 and four upper external terminals 904 respectively connected to the four upper electrodes 902 are formed in a top surface 901a of a dielectric 901 (see FIG. 21A). Incidentally, the four upper electrodes 902 and the four upper external terminals 904 are arranged at equal intervals along a longitudinal direction of the capacitor array.
In addition, four lower electrodes 903 and four lower external terminals 905 respectively connected to the four lower electrodes 903 are formed in a bottom surface 901b of the dielectric 901 (see FIG. 21B). Incidentally, the respective lower electrodes 903 are arranged in a position opposed to the corresponding upper electrodes 902 formed in the top surface 901a of the dielectric 901 with the dielectric 901 interposed between the lower electrodes 903 and the upper electrodes 902.
In the example shown in FIGS. 21A to 21C, two central upper external terminals 904 formed in the top surface 901a of the dielectric 901 are connected to each other by an upper wiring electrode 906. In addition, on the surface of FIG. 21B, two lower external terminals 905 on a left side which external terminals are formed in the bottom surface 901b of the dielectric 901 are connected to each other by a lower wiring electrode 907, and two lower external terminals 905 on a right side which external terminals are formed in the bottom surface 901b of the dielectric 901 are connected to each other by a lower wiring electrode 908. By thus connecting each external terminal by a wiring electrode, four variable capacitors respectively formed between the four upper electrodes 902 and the four lower electrodes 903 are connected in series with each other (see FIG. 21C).
The configuration as shown in FIGS. 21A to 21C can reduce the number of external terminals with respect to the number of capacitors, and provides the following effects. By connecting the four capacitors in series with each other, an alternating voltage applied to each variable capacitor is decreased, and the withstand voltage characteristic of the element is improved. In addition, variations in characteristics such for example as the capacitance and Q-value (Quality of factor) of the element as a whole according to the alternating voltage are reduced. In addition, when the distance between the external terminals is increased, discharge between the terminals can be suppressed. Further, because the plurality of capacitors are fabricated en bloc, characteristic variations of each variable capacitor can be reduced.